The present invention relates generally to phase locked loops, and more particularly, to a phase locked loop having memory.
Current phase lock loop algorithms are almost exclusively analog in nature (using an operational amp to perform a comparison, i.e., a VCO) and determine the clock period adjustment based on a single measurement at the time a reference clock edge occurs (no historical information is kept and no attempt is made to use historical information to influence the decision). Such systems are subject to very large phase errors and are heavily influenced by random noise. Due to their analog nature, such systems are also difficult to highly integrate (for example with a divide by K function or with a highly desirable reference edge registration feature of the present invention). Such analog systems are also relatively susceptible to loss of phase lock or incapability of obtaining phase lock, due to random variations in the system (i.e. voltage noise). The implementation of the present invention results in relatively small phase errors, high integration, and robustness to random variations (system noise).
The motivation for the development of the present invention is to allow clock phase locked loop frequency and phase matching (locking) to a finer resolution bounded by a smaller maximum phase error) than has heretofore been practical to achieve. The advantages of the teachings of the present invention include extremely accurate delay approximation to the reference clock frequency, bounding of phase error adjustments, robustness to short lived transients (such as voltage noise), and registration to the reference clock edge (when it occurs).
Accordingly, it is an objective of the present invention to provide for a phase locked loop having memory that allows clock phase locked loop frequency and phase matching (locking) to a finer resolution than prior devices as well as filtering of the effects of short lived instantaneous noise.